The present invention relates generally to an etching system for etching wafers of a semiconductor material, such as may be used in the fabrication of integrated circuits, and more particularly to an improved system using an aerosol centrifuge etching (ACE) technique.
In one known method of fabricating integrated circuits, a wafer having a semiconductive substrate layer and an outer oxide film layer is prepared for etching in the following manner. An etchant reactable with the oxide film, but not with the semiconductor substrate layer, is selected. A polymer coating is placed over the oxide layer. The polymer chosen is resistant to the selected etchant until exposed to ultraviolet (UV) light. A mask defining a fine line pattern is placed over the polymer coating, and the wafer is exposed to a UV light source to form a pattern in the polymer coating of irradiated etchable regions and shielded nonetchable. The mask is then removed from the wafer.
During etching of the prepared wafer, the etchant removes the exposed regions of the polymer coating and the oxide film layer beneath these regions while, in theory, the masked regions of the polymer coating shield the oxide film layer therebeneath from being removed by the etchant. After etching, the remaining polymer coating is removed. Ideally, the etched wafer has a contoured pattern of raised lands or plateaus of the oxide film separated by depressions extending downwardly to the semiconductive substrate layer. Fabrication may be continued by placing an additional oxide film layer or a semiconductive material layer, such as that doped with positive or negative ions, over the etched surface. The coating, masking and etching steps may then be repeated. In this manner, the layers of an integrated circuit wafer may be formed.
Several known dry etching techniques capable of a high fidelity transfer of fine line patterns may be used in the fabrication of integrated circuits, and particularly in the manufacture of large industrial wafers, such as very large scale integrated (VLSI) and ultra large scale integrated (ULSI) circuits. For example, ion beam milling and sputter etching are each nonreactive dry etching techniques which are anisotropic, that is, possessing a high degree of directionality. However, dry etching methods have a low selectivity, that is, the etching proceeds beyond the desired region into the substrate layer and into the masked regions of the polymer layer. This low selectivity renders the dry techniques particularly unsuitable for etching multilayer wafers.
Another dry etching technique is plasma etching, wherein certain activated gaseous species generated in plasma are applied to a patterned surface to etch the wafer. Plasma etching is anisotropic and has improved selectivity over the ion beam milling and sputter etching techniques. Presently, plasma etching is the dominant technique for use in VLSI fabrication. However, plasma etching suffers from several disadvantages, such as radiation damage to the finished product, the production of contaminants, process control problems, and high cost.
Another known etching technique which may be used in the fabrication of integrated circuits is wet chemical etching. Wet chemical etching is a conventional technique wherein the prepared wafers to be etched are dipped in a bath of etchant liquid. The conductive currents within the etchant liquid transport the etchant to and the reaction products from the wafer. The wet etching technique has several advantages over the plasma etching technique, including lower cost, ease of control, versatility and higher selectivity than plasma etching.
The wet etching technique suffers from several disadvantages, such as contamination of the etchant liquid from contaminants introduced into the bulk liquid etchant. However, the most severe limitation of wet etching is the incapability of the technique to produce extremely fine line patterns in wafers, such as those required in the fabrication of VLSI circuit wafers. This limitation stems from a lack of anisotropy, which is manifested as undercutting.
In the ideal case, the etching of a prepared wafer proceeds in a direction normal to the polymer outer surface, forming a trough with straight sidewalls. However in practice, due to the isotropic nature of the region between the wet chemical etchant and the material being etched, the etching reaction also proceeds outwardly into the sidewalls of the trough being etched. This results in the etchant removing portions of the oxide layer beneath the masked regions of the polymer coating.
For example, the wet etching technique is illustrated in FIGS. 1(a) through 1(d) by cross sectional views of a wafer W being etched. In FIG. 1(a), a prepared wafer W is shown having a semiconductive substrate layer S over which an etchable oxide film layer X has been formed. An irradiated polymer coating layer P having an outer surface F covers the oxide layer X. The irradiated polymer layer P has plural nonetchable regions M which were covered by a mask during irradiation, and plural irradiated etchable regions R which have been irradiated by exposure to a UV light source.
In FIG. 1(b), the etchant liquid L is shown etching through the irradiated regions R of the polymer layer P. In FIG. 1(c), the liquid etchant L is shown etching downwardly through the oxide layer X to form a trough T. The etchant L undercuts the sidewalls of trough T, as indicated by the letter U, with the undercutting extending under the nonetchable, masked region M of the polymer layer P.
FIG. 1(d) illustrates the final product upon completion of the wet etching process. Due to the undercutting, plateaus remain which have only minimal amounts of the oxide layer X. The minimal cross sectional area of oxide layer X may cause excessive heating of the finished product during use, with a subsequent decrease in the reliability of the finished product. In the extreme case, as the distance between two adjacent troughs is decreased, the two troughs may actually merge. Thus, fine line pattern formation in submicron size, as required for VLSI and ULSI wafers, is extremely difficult using wet etching.
Another etching technique has been proposed by researchers at the University of Texas, and is referred to as Aerosol Jet Etching (AJE). See Y. Chen, J. Brock and I. Trachtenberg, "Aerosol Jet Etching of Fine Patterns," Applied Physics Letters, Vol. 51, No. 26, pp. 2203-05 (American Institute of Physics, 1987). In the AJE process, a gas which contains an etchant vapor is adiabatically expanded by an expansion nozzle to form fine droplets or aerosols of etchant. A aerosol jet having a conical pattern with a central jet axis is formed upon leaving the expansion nozzle. A surface to be etched is located a spaced-apart distance away from the expansion nozzle outlet and positioned normal to the jet axis. The fine etchant droplets or aerosols are carried by the expanding aerosol jet from the expansion nozzle to impinge upon the surface to be etched.
The AJE method is illustrated in FIGS. 2(a) through 2(d), as applied to a waver W prepared as explained for FIG. 1. In FIG. 2(b), etchant aerosols A are shown etching through the irradiated regions R of the polymer layer P. Despite a rather complicated gas flow pattern, the researchers of the AJE technique have performed a comprehensive hydrodynamic study of the technique. This study shows that the aerosol movement is reasonably perpendicular to outer surface F of polymer layer P, as indicated by arrow B.
In FIG. 2(c), the aerosol A is shown etching through the oxide layer X to form trough T, while the finished product is shown in FIG. 2(d). The etchant aerosols which impinge on the sidewalls of the trough T do not drain away. Some etchant aerosols cling to the trough sidewalls causing a certain degree of undercutting U although such undercutting is not as severe as that occurring with wet etching (compare FIGS. 1(d) and 2(d)). Furthermore, the surface tension of the aerosol restricts the etchant from spreading uniformly on the bottom surface of the trough T resulting in localized etching or pitting. Pitting produces a variety of undesirable effects on subsequent fabrication steps.
The AJE technique is impractical for processing large industrial wafers, which may be several inches in diameter. Processing of such a large wafer requires scanning the aerosol jet over the entire area of the surface to be etched. Such scanning produces nonuniform etching due to the conical spreading pattern of the aerosol jet.
For example, the direction of aerosol movement near the jet axis is substantially perpendicular to the surface of the specimen to be etched. However, the aerosols at the outer periphery of the aerosol jet impinge upon the surface to be etched at angles other than 90.degree. which produces nonuniform etching. Thus, the AJE method is incapable of etching a large area at a uniform rate to produce uniform etching over the entire surface area, such as is required to etch a large industrial wafer.
Thus, a need exists for an improved etching system for producing integrated circuit wafers, and particularly for processing large industrial wafers, which is not susceptible to the above limitations and disadvantages.